Substrate inspecting devices for inspecting substrates by capturing images from a plurality of video cameras have been developed in order to inspect whether or not there are defects in manufactured products such as substrates. For example, Japanese Unexamined Patent Application Publication H6-222011 (“JP '011”) discloses a substrate inspecting device that uses a video signal that performs interlacing alternating between odd frames and even frames. In this substrate inspecting device, horizontal synchronization signals that are offsetted by ½ the horizontal synchronization period are applied to each of a set of mutually-facing video cameras, where odd-frame images are captured by one video camera set, and even frame images are captured by the other video camera set. Doing so enables continuous and high-speed analysis of inspection regions of manufactured products.
However, in the substrate inspecting device as set forth in JP '011, it is necessary to control the timing of the imaging in the plurality of video cameras based on a synchronization signal. If an attempt were made to control the timing of the activation of the individual video cameras without connections for supplying the synchronization signals, then time measuring means, such as a counter, would have to be used, and the timing of activation would have to be controlled based on the counting value of the counter.
In activation control using such a counter, a register is assigned to each device, and the control of the timing of activation for the devices is performed based on the register counts. For example, after the counter is activated, an operation is repeated wherein the number of the specific register is changed each time a specific count elapses, to measure the passage of time, where the counting is ended when the register count goes to zero, or the like, indicating that a specific amount of time has elapsed since the commencement of counting. Once the counting of the elapsed time by the counter has ended, then this must be detected without delay, and activating data must be written to the register without delay to reactivate the counter.
However, because it is necessary for the reading and writing of registers by the controlling circuit to be performed sequentially for each register, in some cases there will be a substantial delay in the timing with which the data of the register is read after the register count has reached zero. If the detection of the end of counting in any of the counters is delayed, then the timing of the reactivation will be late, preventing the commencement of the image capturing from being performed with the correct timing.
Given this, one object of the present invention is to provide a device controlling unit and CPU (central processing unit) able to operate without delay even when there is a plurality of devices that are not synchronized to each other.